An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz
This paper presents a voltage reference (VR) with a power supply rejection (PSR) better than 50 dB for frequencies of up to 60 MHz, and uses MOSFETs in strong inversion. Another innovation is a compact MOSFET low-pass filter, which was developed along with a feedback technique for a wide-bandwidth PSR not achieved in previous works. The proposed all-MOSFET VR was fabricated using a standard 0.18µm CMOS process. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
Subthreshold-based MOSFET (STBM) VRs, compared with BGRs, have an inherent advantage in power consumption. However, due to the effects of the temperature-dependent gate-to-surface coupling coefficient m, poor transistor ratio matching, and the inaccuracies of models, designing STBM VRs is usually an inexact process, resulting in inferior performance. Furthermore, it is difficult to achieve compact and low noise VRs due to either lack of accurate models or low sheet resistance in digital CMOS processes. For modern SoC applications, it is necessary for embedded VRs to have high power supply rejection (PSR) over a wide frequency bandwidth in order to reject noise from the high-speed on-chip digital circuits. Conventional techniques, such as using long channel lengths, cascade structures, and pre-regulations, are usually adopted in VRs to improve PSR. However, such techniques can only improve the low frequency performance at the expense of headroom, area, and power dissipation. A resistorless low-power non-band-gap VR is presented in this paper. All the MOSFETs in the core are standard CMOS transistors biased in strong inversion. Using strong inversion, we used some extra power compared with the weak inversion designs. However, we achieved a more accurate reference since using strong inversion leads to better transistor ratio matching compared with using weak inversion. In the proposed VR, a proportional-to-absolute-temperature (PTAT) voltage is converted into current (I) proportional to mobility (μ) and the square of temperature (T2), i.e., I ∝μT2. This current is used to extract a temperature stable reference voltage from the VGS of a diode-connected nMOS. In addition to a compact all-MOSFET passive lowpass filter (LPF), a feedback technique is also proposed for wide bandwidth PSR enhancement. The VR is fabricated in a standard 0.18μm CMOS process.
- Design is fixed
- Low performance
The conceptual block diagram of the proposed VR circuit is shown in Fig. 1. A PTAT voltage is generated using a PTAT voltage generator and converted into a current proportional to μT2, which serves as a bias current for the whole VR.
Figure 1: Conceptual block diagram of the proposed VR circuit. The PTAT voltage generator puts forth the voltage needed to convert to a bias current for the whole VR. Finally, a diode-connected nMOS transistor (active load) is used to generate a temperature-independent reference
A 5-bit trimming is applied to the output current to cancel the effects of process variation. Also, in order to compensate for the unwanted parasitic diode leakage current at high temperatures, a temperature compensation branch is introduced to increase the output bias current at high temperatures. The PTAT voltage generator, theV-to-I converter, and the feedback form a self-biased current source. The feedback in a self-biased current source is used to provide feed forward and feedback paths for PSN. The feedback and feed forward paths enhance the PSR performance of the VR up to medium range frequency. The passive LPF is a compact all-MOSFET LPF used to attenuate the supply noise at high frequencies.
PTAT Voltage Generator:
The minimum supply voltage in most VRs is dependent on the reference output voltage. Hence, a simple way to decrease the minimum supply voltage of a VR circuit is to reduce the reference’s output voltage. In BGRs, this can be done either by making sure that only a fraction of the material bandgap affects the circuit or by lowering the material bandgap. The latter is not feasible in standard CMOS technologies, but the former solution is practical and can be implemented in several ways. The most power efficient and compact technique for low power, low-voltage BGR design is to virtually lower the material bandgap using an electrostatic field. By this, the circuit “senses” a bandgap, which is the material bandgap lowered by the electrostatic field. To implement this method, one has to replace the conventional bipolar junction transistor (BJT) with a dynamic threshold MOS transistor (DTMOS).
Figure 2: (a) Cross section of a DTMOS transistor and schematic connection. (b) PTAT generation from DTMOS. (c) Simulated temperature characteristics of DTMOS and corresponding PTAT voltage.
A cross section of DTMOS is shown in Fig. 2(a). As can be seen, this device is a standard pMOS transistor with an interconnected body and gate, and its operation is similar to a BJT or a weak-inversion MOS operation; hence, it can be viewed as a lateral BJT with an extra gate over the base or as an MOS whose threshold voltage is dynamically controlled by the VGS voltage.
Self-Biased Current Source:
The self-biased current source serves as the core of the proposed VR and consists of an asymmetric source-input voltage to-current converter (formed by transistors MN1,MN2,MP1, and MP2), the PTAT voltage generator from the DTMOS1 and DTMOS2, and a feedback branch (consisting of DTMOS0, MN0, and MP0). In Fig. 3, the asymmetric source-input voltage-to-current converter (transconductance) is used to convert the PTAT voltage from the DTMOS into a bias current for the VR. In addition to minimizing the voltage difference between nodes A and B, the feedback is also used to realize a partial feed forward transfer function for PSN.
Figure 3: Proposed VR circuit
A startup circuit (formed by MS1-MS3 as shown in Fig. 3) is used to ensure that the former state is achieved. At startup, the transistor MS1 is OFF since VREF is zero. This makes the voltage across MOSFET capacitor MS1 zero; hence, the node H is pulled up to VDD.Asaresult,MS3 is turned ON, pulling down node G and thereby allowing IBIAS to flow.
Figure 4: Leakage compensation configuration. (a) Low temperature. (b) High temperature.
A thermal switch, formed by transistors MN4, MN5, and MP6 is used to allow ICOMP(copied multiple of IBIAS) to flow into the drain MN3 to compensate for the leakage current. The MN5, with its gate connected across VDTMOS1,isOFFat low temperatures (below 50 °C) since its threshold voltage at these temperatures is higher than VDTMOS1. As a result, MP6 is also OFF, hence cutting off ICOMP. MN5 gradually begins to turn on as the temperature increases because VTH decreases faster with a temperature rise compared to the VDTMOS1. MP6 is progressively turned ONas the temperature increases since its gate voltage is slowly lowered. This allows ICOMP to steadily increase to compensate for the leakage current as the temperature increases. Fig. 4(a) and (b) illustrates the active load and leakage compensation circuit configuration for low and high temperature operations, respectively.
- Design flexibility
- High performance
- Tanner tool