VLSI IEEE TRANSACTION – 2017-18
LOW POWER
HIGH SPEED DATA TRANSMISSION
AREA EFFICIENT/ TIMING & DELAY REDUCTION
Audio, Image and Video Processing
VERIFICATION
41 | COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits |
42 | Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction |
NETWORKING
43 | Multicast-Aware High-Performance Wireless Network-on-Chip Architectures |
VLSI – BACK END PROJECT – TANNER(nm) / HSPICE(nm) / DSCH3 – MICROWIND(um)