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IEEE VLSI 2016-2017

1. A 0.521 V Fast Lock-In Adpll For Supporting Dynamic Voltage And Frequency Scaling
2. A 3-D Cpu-Fpga-Dram Hybrid Architecture For Low-Power Computation
3. A 520k (18 900, 17 010) Array Dispersion Ldpc Decoder Architectures For Nand-Flash Memory
4. A Cellular Network Architecture With Polynomial Weight Functions
5. A Configurable Parallel Hardware Architecture For Efficient Integral Histogram Image Computing
6. A Dynamically Reconfigurable Multi-Asip Architecture For Multistandard And Multimode Turbo Decoding
7. A Fast Fault-Tolerant Architecture For Sauvola Local Image Thresholding Algorithm Using Stochastic Computing
8. A Fast-Acquisition All-Digital Delay-Locked Loop Using A Starting-Bit Prediction Algorithm For The Successive-Approximation Register
9. A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled Dpwm
10. A Fully Digital Front-End Architecture For Ecg Acquisition System With 0.5 V Supply
11. A High Throughput List Decoder Architecture For Polar Codes
12. A High-Performance Fir Filter Architecture For Fixed And Reconfigurable Applications
13. A High-Speed Fpga Implementation Of An Rsd-Based Ecc Processor
14. A High-Throughput Hardware Design Of A One-Dimensional Spiht Algorithm
15. A Low-Power Broad-Bandwidth Noise Cancellation Vlsi Circuit Design For In-Ear Headphones
16. A Mixed-Decimation Mdf Architecture For Radix-2k Parallel Fft
17. A New Binary-Halved Clustering Method And Ert Processor For Assr System
18. A New Cdma Encodingdecoding Method For On-Chip Communication Network
19. A New Optimal Algorithm For Energy Saving In Embedded System With Multiple Sleep Modes
20. A New Parallel Vlsi Architecture For Real-Time Electrical Capacitance Tomography
21. A Normal Io Order Radix-2 Fft Architecture To Process Twin Data Streams For Mimo
22. A Novel Quantum-Dot Cellular Automata X-Bit X 32-Bit Sram
23. A Performance Degradation Tolerable Cache Design By Exploiting Memory Hierarchies
24. A Single-Stage Low-Dropout Regulator With A Wide Dynamic Range For Generic Applications
25. A Systematic Design Methodology Of Asynchronous Sar Adcs
26. Algorithm And Architecture Of Configurable Joint Detection And Decoding For Mimo Wireless Communications With Convolution Codes
27. An Add-On Type Real-Time Jitter Tolerance Enhancer For Digital Communication Receivers
28. An All-Digital Approach To Supply Noise Cancellation In Digital Phase-Locked Loop
29. An Efficient Single And Double-Adjacent Error Correcting Parallel Decoder For The (24,12) Extended Golay Code
30. Area-Aware Cache Update Trackers For Postsilicon Validation
31. Argo A Real-Time Network-On-Chip Architecture With An Efficient Gals Implementation
32. Code Compression For Embedded Systems Using Separated Dictionaries
33. Concept, Design, And Implementation Of Reconfigurable Cordic
34. Design And Fpga Implementation Of A Reconfigurable 1024-Channel Channelization Architecture For Sdr Application
35. Design And Implementation Of High-Speed All-Pass Transformation-Based Variable
36. Digital Filters By Breaking The Dependence Of Operating Frequency On Filter Order
37. Design Of A Cmos System-On-Chip For Passive, Near-Field Ultrasonic Energy Harvesting And Back-Telemetry
38. Design Of A Network Of Digital Sensor Macros For Extracting Power Supply Noise Profile In Socs
39. Design Of Modified Second-Order Frequency Transformations Based Variable Digital
40. Filters With Large Cutoff Frequency Range And Improved Transition Band Characteristics
41. Design Of Silicon Photonic Interconnect Ics In 65-Nm Cmos Technology
42. Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization
43. Dual-Calibration Technique For Improving Static Linearity Of Thermometer Dacs For Io
44. Efficiency Enablers Of Lightweight Sdr For Mimo Baseband Processing
45. Efficient Dynamic Virtual Channel Organization And Architecture For Noc Systems
46. Efficient Synchronization For Distributed Embedded Multiprocessors
47. Emdbam A Low-Power Dual Bit Associative Memory With Match Error And Mask Control
48. Energy-Efficient Floating-Point Mfcc Extraction Architecture For Speech Recognition Systems
49. Enhanced Wear-Rate Leveling For Pram Lifetime Improvement Considering Process Variation
50. Error Resilient And Energy Efficient Mrf Message-Passing-Based Stereo Matching
51. Exploiting Intracell Bit-Error Characteristics To Improve Min-Sum Ldpc Decoding For Mlc
52. Nand Flash-Based Storage In Mobile Device Exploiting Intracell Bit-Error Characteristics To Improve Min-Sum Ldp
53. Fault Tolerant Parallel Ffts Using Error Correction Codes And Parseval Checks
54. Fcuda-Noc A Scalable And Efficient Network-On-Chip Implementation For The Cuda-To-Fpga Flow
55. Fixed-Point Computing Element Design For Transcendental Functions And Primary Operations In Speech Processing
56. Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic
57. Flexible Ecc Management For Low-Cost Transient Error Protection Of Last-Level Caches
58. Floating-Point Butterfly Architecture Based On Binary Signed-Digit Representation
59. Glitch Energy Reduction And Sfdr Enhancement Techniques For Low-Power Binary-Weighted Current-Steering Dac
60. Gpu-Accelerated Parallel Sparse Lu Factorization Method For Fast Circuit Analysis
61. Graph-Based Transistor Network Generation Method For Supergate Design
63. Hardware And Energy-Efficient Stochastic Lu Decomposition Scheme For Mimo Receivers
64. High-Performance Nb-Ldpc Decoder With Reduction Of Message Exchange
65. High-Performance Pipelined Architecture Of Elliptic Curve Scalar Multiplication Over Gf(2m)
66. High-Speed And Energy-Efficient Carry Skip Adder Operating Under A Wide Range Of Supply Voltage Levels
67. Hybrid Lutmultiplexer Fpga Logic Architectures
68. Implementing Minimum-Energy-Point Systems With Adaptive Logic
69. In-Field Test For Permanent Faults In Fifo Buffers Of Noc Routers
70. Incorporating Process Variations Into Sram Electro Migration Reliability Assessment Using Atomic Flux Divergence
71. Input-Based Dynamic Reconfiguration Of Approximate Arithmetic Units For Video Encoding
72. Integrated Floating-Gate Programming Environment For System-Level Ics
73. Knowledge-Based Neural Network Model For Fpga Logical Architecture Development
74. Low-Cost High-Performance Vlsi Architecture For Montgomery Modular Multiplication
75. Low-Power Ecg-Based Processor For Predicting Ventricular Arrhythmia
76. Low-Power Fpga Design Using Memoization-Based Approximate Computing
77. Low-Power Split-Radix Fft Processors Using Radix-2 Butterfly Units
78. Low-Power System For Detection Of Symptomatic Patterns In Audio Biological Signals
79. Low-Powercost Rns Comparison Via Partitioning The Dynamic Range
80. Lut Optimization For Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
81. Measuring Improvement When Using Hub Formats To Implement Floating-Point Systems Under Round-To-Nearest
82. Memory-Aware Loop Mapping On Coarse-Grained Reconfigurable Architectures
83. Nand Flash Memory With Multiple Page Sizes For High-Performance Storage Devices
84. Network-On-Chip For Turbo Decoders
85. On Efficient Retiming Of Fixed-Point Circuits
86. One-Cycle Correction Of Timing Errors In Pipelines With Standard Clocked Elements
87. Online Measurement Of Degradation Due To Bias Temperature Instability In Srams
88. Optimized Built-In Self-Repair For Multiple Memories
89. Peva A Page Endurance Variance Aware Strategy For The Lifetime Extension Of Nand Flash
90. Power Efficient Level Shifter For 16 Nm Finfet Near Threshold Circuits
91. Proceed A Pareto Optimization-Based Circuit-Level Evaluator For Emerging Devices
92. Process Variation Delay And Congestion Aware Routing Algorithm For Asynchronous Noc Design
93. Read Bitline Sensing And Fast Local Write-Back Techniques In Hierarchical Bitline Architecture For Ultralow-Voltage Srams
94. Rf Power Gating A Low-Power Technique For Adaptive Radios
95. Source Code Error Detection In High-Level Synthesis Functional Verification
96. Source Coding And Pre-Emphasis For Double-Edged Pulse Width Modulation Serial Communication
97. Test Escapes Of Stuck-Open Faults Caused By Parasitic Capacitances And Leakage Currents
98. The Vlsi Architecture Of A Highly Efficient Deblocking Filter For Hevc Systems
99. Toward Solving Multichannel Rf-Soc Integration Issues Through Digital Fractional Division
100. Ultralow-Energy Variation-Aware Design Adder Architecture Study
101. Understanding The Relation Between The Performance And Reliability Of Nand Flashscm Hybrid Solid-State Drive
102. Unequal-Error-Protection Error Correction Codes For The Embedded Memories In Digital Signal Processors