A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission
This paper presents a full active rectifier consisting of GaN devices and a CMOS controller designed for wireless power transmission in high-power consumer devices. An adaptive time delay control circuit is developed to maximize the conduction interval of the GaN switch, which can significantly reduce the power loss caused by the forward voltage imposed by the diode. The proposed control algorithm also eliminates the reverse leakage current of the rectifier, and thus further improves its power transfer efficiency. The controller implemented based on a highvoltage 0.18-µm CMOS process and the power stage consisting of four GaN transistors are assembled on the same printed circuit board (PCB) board. The proposed rectifier provides a maximum output current of 3 A at 5 V, with a 6.78-MHz ac input voltage. Its peak power transfer efficiency is 91.8%. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
Full-wave rectifiers are widely used for wireless power transfer applications, because of their high voltage conversion ratio. In general, full-wave rectifiers can be divided into three categories: 1) passive rectifiers with four diodes; 2) half active rectifiers; and 3) full-active rectifiers. For 1) and 2), the forward voltage of the diode limits the power conversion efficiency (PCE) and voltage conversion ratio of the rectifier. For 3), four power transistors are used as four respective switches with small ON-state resistance, hence having a much lower power loss than that of the diodes. However, the techniques used for milliamps applications are not suitable for high power applications because of the larger capacitances of the transistors. Delay locked loop (DLL) based on a voltage controlled delay circuit can be used to solve this problem. To compensate for the delay of the gate driver, a replica delay unit has to be used in the DLL structure. Since the design is intended for high power application, the driver transistor itself can be very large; hence, such a replica unit would cause significant area overheads. Meanwhile, the replica unit and large numbers of voltage controlled time delay unit would cause the matching problem and cause potential reverse loss.A time delay compensation technique with sampling of the reverse current is used to control the comparator. This technique is based on the existence of reverse current in the first place. Nonetheless, this is not acceptable for high power applications since a high reverse current would cause damage to the power transistor.
- Power consumption is high
We describe a digital adaptive time delay (ATD) controller based on successive approximation registers (SAR) algorithm to solve the above-mentioned problems. This solution is capable of extending the active duration of the rectifier while eliminating the reverse leakage.
Figure 1: Topology and operation of the proposed full-active rectifier in the positive half-cycle. (a)VH<Vth .(b)Vth <VH<VREC.(c)VREC<VH.
Structure and Operating Principles of the Proposed Rectifier:
The topology and operating principle of a basic cross connected full active rectifier with the proposed ATD controller is shown in Fig. 1. The magnetic flux arising from the PA produces an ac voltage, VAC.CDC denotes the dc smoothing capacitor and RL is the load resistor. Unlike the tradition cross-coupled rectifier with two PMOSFETs and two NMOSFETs, GaN transistors (N1–N4)are used for their lower ON-resistance and lower input capacitance. N3 andN4 are connected in a cross-coupled configuration controlled directly by VH(VL). In addition, to avoid the reverse leakage current from the load to the ac input source, another two GaN transistors,N1 and N2, are used and controlled by an ATD controller, which turns ONN1 and N2 only when VH(VL) is larger than VREC. The ATD controller monitors and controls the time difference between the gate drive signals (VG1 and VG2) and the input voltages (VH and VL). An SAR algorithm is employed to maximize the conduction time of N1 andN2 to enhance the efficiency.
Figure 2: Details of the ATD control
Adaptive Time Delay Control Algorithm:
Fig. 2 shows the topology of the proposed rectifier with the ATD controller, and Fig. 3 shows the timing diagram of the controller. In the proposed rectifier, the duty cycle of the gate drive signal td(n) of N1 and N2 is adjusted to compensate for the propagation time of the gate driver such that the transistor will be turned OFF exactly when VH(VL) decreases to VREC, to remove the reverse current. A controller is used to detect the time difference between the transistor shut OFFtime and the moment when VH(VL) decreases to VREC, which is represented by∆t, as shown in Fig. 4. A successive approximation feedback algorithm is utilized to control the duty cycle of the transistor.
Figure 3: Details of the ATD control
Topology of the Proposed Rectifier:
The proposed active rectifiers along with all detailed blocks are illustrated in Fig. 4. The ATD controller marked in red dashed lines as shown in Fig. 4 was fabricated based on a 0.18-μm high-voltage Austria microsystems (AMS) process. The GaN power transistors (N1–N4) are not incorporated in this chip design due to the integrability issues. As described earlier, the lower side GaN FETs (N3 andN4)are self-turned ON/OFF by the ac input voltage, whereas the upside GaN FETs (N1 andN2)are controlled by the ATD controller. The ATD controller consists of an SAR feedback circuit, a fixed time delay unit, and an adjustable time delay unit. ForN1 andN2, level shifters and bootstrap circuit are used to boost the voltage of the gate signal. The gate drive circuit is used to provide a large gate charging/discharging current for GaN devices.
Figure 4: Topology of the proposed rectifier with detailed blocks.
- Power consumption is low
- Tanner tool