Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
A conditional-boosting flip-flop is proposed for ultra-low voltage application where the supply voltage is scaled down to the near-threshold region. The proposed flip-flop adopts voltage boosting to provide low latency with reduced performance variability in the near threshold voltage region. It also adopts conditional capture to minimize the switching power consumption by eliminating redundant boosting operations. Experimental results in a 65-nm CMOS process indicated that the proposed flip-flop provided up to 72% lower latency with 75% less performance variability due to process variation, and up to 67% improved energy-delay product at 25% switching activity compared with conventional precharged differential flip-flops. The proposed architecture of this paper is analysis the logic size, area and power consumption using tanner tool.
Capacitive boosting can be a solution to overcome theproblems caused by aggressive voltage scaling. It allows the gatesource voltage of some MOS transistors to be boosted above thesupply voltage or below the ground.The enhanced driving capabilityof transistors thus obtained can reduce the latency and its sensitivityto process variations. The bootstrapped CMOS driver presentedin  relies on this technique to drive heavy capacitive loads withsubstantially reduced latency. However, since it is a static driver,every input transition causes the bootstrapping operation. So, ifsome of the transitions are redundant, a large amount of redundantpower consumption may occur. The conditional-bootstrapping latchedCMOS driver  proposes the concept of conditional bootstrappingto eliminate the redundant power consumption. As it is a latcheddriver, it can allow boosting only when the input and output logicvalues are different, resulting in no redundant boosting and improvedenergy efficiency, especially at low switching activity. Recently, adifferential CMOS logic family adapting the boosting technique hasalso been proposed for fast operation at the near-threshold voltageregion.
- Low speed
- Less performance
For incorporating the conditional boosting into a precharged differential flip-flop, four different scenarios regarding input data capture should be considered, which are determined by the logic states of the input and output. These scenarios are as follows:
- For a low output data, a high input data should trigger boosting for a fast capture of incoming data;
- For a low output data, a low input data should trigger no boosting since the input need not be captured;
- For a high output data, a low input data should trigger boosting for a fast capture of incoming data;
- For a high output data, a high input data should trigger no boosting.
These scenarios can be embodied into a circuit topology usinga single boosting capacitor by a combination of two operationprinciples. One is that the voltage presetting for the terminals ofthe boosting capacitor must be determined by the data stored at theoutput (so-calledoutput-dependent presetting). The other principle isthat boosting operations must be conditional to the input data givento the flip-flop (so called input-dependent boosting). The conceptualcircuit diagrams for supporting these principles are shown in Fig. 1.To support the output-dependent presetting, the preset voltages ofcapacitor terminalsNandNBare made to be determined by outputsQandQBas shown in Fig. 1(a). If QandQBare low and high,NandNBare preset to be low and high [left diagram in Fig. 1(a)],and ifQandQBare high and low,NandNBarepresettobehighandlow [right diagram in Fig. 1(a)], respectively. To support the inputdependent boosting, the non-inverting input (D) is coupled to NBthrough an nMOS transistor and the inverting input (DB) is coupledto Nthrough another nMOS transistor, as shown in Fig. 1(b). Then,as one case in which a low data is stored in the flip-flop, resulting
in the capacitor presetting given in the left diagram in Fig. 1(a),a high input allows NBto be pulled down to the ground, lettingNbeing boosted toward–VDDdue to capacitive coupling [upperleft diagram in Fig. 1(b)]. Meanwhile, a low input allows Ntobe connected to the ground, but since the node is already presetto VSS, there is no voltage change at NB, resulting in no boosting[lower left diagram in Fig. 1(b)]. As the other case in which a highdata is stored in the flip-flop, resulting in the capacitor presettinggiven in right diagram in Fig. 1(a), a low input allows Nto bepulled down to the ground, letting NBbeing boosted toward –VDDdue to capacitive coupling [lower right diagram in Fig. 1(b)].
Figure 1: Conceptual circuit diagrams for (a) output data-dependent presetting
Meanwhile, a high input allowsNBto be connected to the ground, butsince the node is already presettoVSS, there is no voltage changeat N, resulting in no boosting [upper right diagram in Fig. 1(b)].Table I summarizes these operations for easier understanding. Withthese operations, any redundant boosting can be eliminated, resulting in a significant power reduction, especially at low switchingactivity.
Table 1: DATA-DEPENDENTPRESETTING ANDBOOSTING
The structure of the proposed conditional-boosting flip-flop (CBFF)based on the concepts described in the previous section is shown inFig. 2. It consists of a conditional-boosting differential stage, a symmetric latch, and an explicit brief pulse generator. In the conditionalboosting differential stage shown in Fig. 2(a), MP5/MP6/MP7and MN8/MN9 are used to perform the output-dependent presetting, whereas MN5/MN6/MN7 with boosting capacitor CBOOTareused to perform the input-dependent boosting. MP8–MP13 andMN10–MN15 constitute the symmetric latch, asshown in Fig. 2(b).Some transistors in the differential stage are driven by a brief pulsedsignal PSgenerated by a novel explicit pulse generator shown inFig. 2(c). Unlike conventional pulse generators, the proposed pulsegenerator has no pMOS keeper, resulting in higher speed and lowerpower due to no signal fighting during the pull-down ofPSB.Theroleof the keeper to maintain a high logic value ofPSBis done by MP1added in parallel with MN1, which also helps a fast pull-down ofPSB.At the rising edge ofCLK, PSBis rapidly discharged by MN1, MP1,and I1, lettingPShigh. After the latency of I2 and I3,PSBis chargedby MP2, and soPSreturns to low, resulting in a brief positive pulseatPSwhose width is determined by the latency of I2 and I3. WhenCLKis low, PSBis maintained high by MP1, although MP2 is OFF.According to our evaluation, the energy reduction is up to 9% forthe same slew rate and pulsewidth.
Figure 2: Proposed CBFF. (a) Conditional-boosting differential stage. (b) Symmetric latch. (c) Explicit brief pulse generator.
- High speed
- High performance
- Tanner EDA