Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

Abstract:

The limited size and power budgets of space-bound systems often contradict the requirements for reliable circuit operation within high-radiation environments. In this paper, we propose the smallest solution for soft-error tolerant embedded memory yet to be presented. The proposed complementary dual-modular redundancy (CDMR) memory is based on a four-transistor dynamic memory core that internally stores complementary data values to provide an inherent per-bit error detection capability. By adding simple, low-overhead parity, an error-correction capability is added to the memory architecture for robust soft-error protection. The proposed memory was implemented in a 65-nm CMOS technology, displaying as much as a 3.5×smaller silicon footprint than other radiation-hardened bitcells. In addition, the CDMR memory consumes between 48% and 87% less standby power than other considered solutions across the entire operating region. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.

Existing System:

One of the primary components of ASICs and FPGAs is static random-access memorys (SRAMs). In accordance with Moore’s Law, the size, density, and power consumption of SRAMs has grown exponentially over the past five decades, often being responsible for over 50% of the total area and static power consumption of modern ASICs. The large area of SRAMs makes them highly susceptible to particle strikes, which are common in high-radiation environments, such as space. Furthermore, modern ASICs are often operated at scaled supply voltages in order to reduce their power consumption. This further reduces the noise margins of SRAMs and significantly increases their susceptibility to radiation effects, such as soft errors caused by single event upsets (SEUs). In order to guarantee reliable memory operation, an additional power supply often must be incorporated, and complex dynamic voltage scaling techniques are sometimes required.

Embedded memory errors are typically handled at either an architectural or circuit level. At the architectural level, redundancy schemes, such as error correction codes (ECCs), dual modular redundancy (DMR), and triple modular redundancy (TMR) are commonly found. However, these solutions are extremely costly in terms of area overhead, while also adding complexity and delay. Therefore, they are not suitable for small, high-speed cache memories such as level-1 (L1) caches. Mohr and Clark suggested using 2-D parity checking and bit interleaving techniques as a solution to this problem. However, conventional architectural solutions do not provide sufficient protection under voltage scaling, which is a common approach to low-power operation. Circuit level techniques such as Dual Interlocked storage

Cell (DICE) and Quatro 10T can efficiently increase SEU tolerance. These solutions achieve SEU tolerance by increasing the internal feedback of the static latch core of a 6-transistor (6-T) bitcell. This approach increases the critical charge (Qcrit) of the bitcell; however, once this value is exceeded, the positive feedback is actually what ensures a bit-flip. Furthermore, these cells feature a much higher transistor count than the traditional SRAM, resulting in upto 2×increase in area and power consumption of the memory array. Therefore, these cells are inefficient for high-speed applications, such as register files and caches that demand full hardening and simplicity.

Disadvantages:

  • Power consumption is high

Proposed System:

We take a completely different and nonintuitive approach to circuit-level SEU tolerance by entirely removing this feedback. We propose to use a dynamic memory core based on GC-eDRAM, which by nature is more susceptible to soft errors than a static memory cell. However, the reduced transistor count and the physical properties of the dynamic circuit allow us to internally apply complementary DMR (CDMR) to achieve inherent per-bit error detection. In addition, the simple addition of parity provides error correction capabilities at a much lower overhead than the traditional ECC-based approaches.

The primary mechanism that enables an SEU to flip the data in a conventional SRAM cell is the positive feedback between the two internal storage nodes. While this feedback is the means by which the static storage capabilities of the circuit are acquired, in the case of SERs, it is also the cell’s vulnerability. Any voltage shift that causes one of the storage nodes to cross the switching threshold of the adjacent inverter will immediately be latched by the positive feedback, resulting in a catastrophic bit flip. Such a voltage shift can be quantified according to the charge transferred by the striking particle, and therefore, the critical charge metric is used to characterize the susceptibility of circuit-level solutions to SEUs. If a particle strike induces charge lower than the Qcrit of the circuit, the storage value will remain intact; however, ifQcrit is exceeded, a failure will occur.

While SRAM is the primary technology used to implement embedded memory arrays, another popular storage topology is eDRAM. GC-eDRAM is a fully logic-compatible implementation of eDRAM, which provides a reduced silicon footprint compared with SRAM, but lacks the internal feedback that ensures strong storage levels, in spite of deteriorating leakage currents. Intuitively, such a topology is much more susceptible to SERs, as the circuit lacks any mechanism to mitigate a level change induced by a particle strike. However, we propose to employ CDMR, i.e., for each bit, to store both the data value and its inverse. Based on this concept, SEUs in the memory array can be both detected and corrected, while still achieving the low area and power aspirations of the target applications.

The proposed CDMR approach is implemented with the 4-T dynamic memory bitcell, illustrated in Fig. 1. The circuit consists of two write transistors (MW1 and MW2), two read transistors (MR1 and MR2), and two storage nodes (SN and SNB). The data and its complementary values are stored on the parasitic capacitances at the storage nodes, comprising the gate capacitance of MR1/MR2 and the diffusion capacitance of MW1/MW2, respectively. Writing to the cell is performed by driving the write word line (to a negative voltage and passing the data and its complementary level from the write bit lines (WBL and WBLB)to SN and SNB, respectively.

Figure 1: Schematic of the proposed 4-T gain cell

Readout is performed by pre-discharging the read bit lines (RBL and RBLB) to Ground and driving the read word line to VDD, thereby charging RBL/RBLB only if SN/SNB holds a data ‘0.’ The RBL/RBLB of each column is connected to a  sensing circuit, which can be implemented with a simple inverter, in order to output the digital levels of the data and its complementary level stored in the selected cell.

IMPLEMENTATION:

The 4-T dynamic memory array was implemented with minimum size in a low-power 65-nm CMOS technology using standard VTp MOS transistors. pMOS transistors were selected as they tend to have less leakage than nMOS transistors, resulting in better retention time characteristics. The use of minimum length devices is not optimal in terms of retention time and/or static power. However, we chose to demonstrate the idea with minimum-sized devices to emphasize that even with this minimal area choice, the proposed solution is efficient. The characteristics of the proposed bitcell could be improved through device upsizing at the expense of additional silicon area. Furthermore, standard VT devices were chosen to demonstrate the general application of the approach even to the most basic and compact circuit design. High-threshold (HVT) devices can further increase the retention time, at the expense of an increased under drive voltage for write assist.

Advantages:

  • Power consumption is low

Software implementation:

  • Tanner tool