Antiwear Leveling Design for SSDs With Hybrid ECC Capability
Abstract:
With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Existing System:
In the past decades, many excellent FTL designs have been proposed to resolve the management issues of Flash memory. Lots of attention was paid to address translation (i.e., address mapping), in which researchers tried to achieve a good compromise between the system performance and the required dynamic RAM (DRAM) space. Due to the rapid deterioration of Flash-memory reliability, WL has also been a highly important research direction in the FTL designs, in which the FTL tries to evenly distribute erases over blocks. WL designs are roughly classified as dynamic or static WL. Dynamic WL (DWL) tries to recycle blocks with invalid pages. Static WL might even migrate (cold) data around so that erases could also be done over blocks of only valid pages, where regular activities are designed to move data round with specially designed limited information, or a way to restrict the potential erases a blocks.
Reliability enhancement is also explored at a lower layer using the ECC technology to manage the growing BER concerns. Stronger capability in ECC recovery usually means higher hardware cost and, most of the time, more space overheads and lower performance. In the past years, it has been an active area in the exploring of better ECC technology to optimize the reliability, performance, and capacity of SSDs. In particular, researchers tried to characterize data patterns and exploit the locality for data errors to occur (and/or then apply some caching ideas. Some proposed to use stronger cells to cover weak cells to lengthen the overall lifetime. Some look-ahead memory sensing idea was proposed with decoding methods to minimize the latency in soft-decision sensing and data transfers. Some advanced ECC designs were proposed to reduce the required redundant parity bits to improve the capacity of Flash-memory devices. More recently, researchers started exploring the possibility in adopting more than one ECC hardware (or hybrid ECC) to improve both performance and reliability. To improve the lifetime, some researches propose to reuses memory pages that contain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage.
Different from the past work in reliability enhancement or hybrid ECC, this paper is motivated by the observation that WL might result in the early performance degradation to SSDs, which commonly go with a limited number of P/E cycles, due to the efforts to delay the BER growth. In particular, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. We shall jointly consider the access patterns and the characteristics of different ECC schemes so as to minimize the performance overheads caused by WL and garbage collection. In contrast to the previous popular approaches, we intend to deliberately generate an uneven WL distribution over blocks. We hope to naturally separate different types of data over sets of blocks to achieve great system performance. At the same time, we aim to hide the performance overheads over the access to blocks of better correction strength. A series of experiments was conducted to evaluate the capability of the proposed design. It was shown that the proposed design could greatly improve the read and write performance by nearly 50% without affecting the system endurance, compared with lowdensity parity-check (LDPC) code approaches. Furthermore, our design can not only provide better performance by hiding the overheads of LDPC but also guarantee the device lifetime with the isolation of hot/cold data.
Disadvantages:
- Area coverage is high
Proposed System:
A hybrid ECC management design to simultaneously consider the I/O performance and reliability of SSDs. Although the hybrid ECC architecture might result in more energy consumption since it adopts two different ECC units. Fig. 1 shows a potential hybrid ECC architecture that consists of the perchannel BCH units and one shared LDPC unit. When the RBER of a block is low, the proposed hybrid ECC uses the BCH mode as its default ECC so as to achieve better read/write performance. A block will be switched to the LDPC mode to gain the longer lifetime while its RBER is rising up. We choose to adopt BCH with the low correction strength and LDPC with the high correction strength. The reason is twofold.
1) The RBER of Flash cells will gradually increase while the number of P/E cycles increases. This means that the need of a higher correction strength ECC is necessary at the later usage stage of SSDs.
2) The gate count of low-strength BCH is relative smaller than that of LDPC.
Figure 1: Hybrid ECC architecture.
Furthermore, in the initial phase, the expected reliability of a block will be not affected by adopting BCH. This is because we use only BCH to encode/decode data while the RBER is low, and switch the block back to LDPC mode when the BCH unit is almost not able to correct the error bits. With the flexibility of two different-strength ECCs, the correction strength can be utilized adaptivity based on the characteristics (i.e., RBER) of the blocks to maximize performance but not affect the device lifetime. As astute readers might point out, the read/write performance of LDPC blocks can be further improved using more gate counts in the hardware design. Note that an LDPC block (respectively BCH block) denotes a block that is supported by LDPC (respectively BCH) for error bit corrections. However, this approach might introduce expensive hardware cost and more energy consumption. Thus, with considering the hardware cost and I/O performance, the considered I/O performance of the shared LDPC unit is worse than that of per-channel BCH units in this paper.
Antiwear leveling design over the hybrid ECC nand flash storage devices:
In this section, an anti-WL design is presented to improve the access performance of SSDs with hybrid ECC capability without sacrificing the reliability of SSDs. With the hybrid ECC capability, the proposed design can avoid the early performance degradation problem caused by WL, that is, to let Flash blocks endure different levels of wears (without the activation of WL), and then exploit the two hybrid ECC properties to have a better compromise between performance and reliability. The two properties are as follows.
1) Flash blocks have a relatively low BER at their early usage stage such that a weak ECC (e.g., BCH) with better encoding/decoding performance is enough.
2) Flash blocks have a relatively high BER at their late usage stage such that a stronger ECC (e.g., LDPC) is required and applied to enhance block reliability.
Figure 2: Overview of the proposed anti-WL management design
The objectives of the proposed design are twofold. The first is to hide the decoding (read) overhead of LDPC blocks. This means that we should efficiently reduce the access rate of LDPC blocks and intelligently select the data stored in LDPC or BCH blocks to take advantage of both BCH and LDPC blocks. The second is to avoid doing WL so as to reduce the performance overhead, since WL might invoke a series of live page copies and garbage collection. Furthermore, evenly distributing wear levels (or erases) to each block will be harmful to the lifespan of BCH blocks. Thus, anantiWL write strategy is proposed to generate an uneven WL distribution over blocks to take advantage of the hybrid ECC module, as shown in Fig. 2. Note that the proposed design is still workable if the strong and weak ECC units (i.e., BCH and LDPC) of the considered hybrid ECC architecture can be replaced with other ECC units (e.g., LDPC with hard decision for the replacement of BCH). Without loss of generality, the number of P/E cycles of each block is used to represent its BER, where a larger (respectively smaller) number of P/E cycles implies a higher (respectively lower) BER in the corresponding block. Note that although blocks of the same Flash chip may have different BERs after enduring the same number of P/E cycles (due to the process variation), the results of some studies show that the number of P/E cycles can still represent the average BER of Flash blocks in a certain degree. Therefore, we will focus our study with P/E cycles and consider process variation as a future work.
Advantages:
- Better performance
- Area coverage is reduced
Software implementation:
- Modelsim
- Xilinx ISE