Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication

by | Oct 24, 2017 | ieee project

Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication

Abstract:

The presence of different noise sources and continuous increase in crosstalk in the deep sub micrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This brief proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as the crosstalk avoidance technique and between hybrid automatic repeat request and forward error correction as the error control policies, three modes of error resiliencies are provided. The results show that, in reduced mode, the scheme achieves up to 25.3% power savings at 3-mm wire length as compared to the original non-adaptive scheme at the cost of only 3.4% power overhead in high protection mode. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

Existing System:

Approaches in handling transient faults for on-chip communication in the presence of various noise sources can beclassified into addressing LVI and TVI faults, individuallyand jointly. Error control schemes like simple parity, cyclicredundancy check, Hamming codes, and Hamming-based product codes were proposed to handle LVI transient faults only, while crosstalk avoidance code schemes and noncodingtechniques including shielding, skewed transition, and repeaterinsertion were proposed to handle TVI only.

On the other hand, a class of work proposed crosstalk-awarecodes that join error control with crosstalk avoidance to addressboth LVI and TVI faults. Earliest schemes, duplicate-add-parity(DAP) , dual rail, boundary shift code, and modifieddual rail code, achieved single error correction (SEC) withreduced worst-case crosstalk-induced bus delay (CIBD) to(1 +2λ)τ0through duplication and parity calculation over data bits.Note thatλis the ratio of wire coupling capacitance to bulkcapacitance andτ0is the crosstalk-free wire delay. Thesecoding schemes achieve the dual function of speeding up bussignal arrival and increasing resilience against single logic levelflips while reducing power consumption.

Recently, more powerful crosstalk-aware codes to detect/correct multibit errors have been proposed to address steadygrowth of noise in ultra-DSM technology. The Hamming product code with skewed transitions achieved multibit error detection; however, it restricted to two errors per row. Acrosstalk avoidance and double error correction scheme wasproposed, encoding the data using Hamming SEC andpassing the resultant codeword into the DAP encoder. This waslater enhanced to the joint crosstalk avoidance and triple errorcorrection (JTEC) scheme and to the JTEC with simultaneousquadruple error detection (JTEC-SQED) scheme. Thishigh error detection/correction enabled a lower voltage swing,thus effectively reducing power while maintaining the targetreliability.

These crosstalk-aware multibit error control codes are designed to achieve target reliability in the presence of worstcase noise conditions predicted, whereas noise level actuallyvaries during operation due to temperature and supply voltage variations. Accordingly, some works attempt to adapt the detection/correction strength based on thenoise level to minimize the power and/or energy consumption.However, they lack the crosstalk-aware capability.

Disadvantages:

  • High power consumption

Proposed System:

The common approach of arbitrarily combining differentcoding schemes leads to a high-complexity design. Theproposed approach exploits the inherent characteristics of jointwire duplication and error control policies, and systematiccodec integration for reduced hardware complexity in providingadaptable error protection levels while maintaining(1+2λ)τ0CIBD.

The proposed scheme works in three modes, i.e., normal mode and two power-saving modes, namely, duplicatedSECDED (D_SECDED), shielded SECDED (S_SECDED),and shielded SEC (S_SEC), respectively. The normal orD_SECDED mode provides the highest error protection atno power saving, while the two power-saving modes (S_SECand S_SECDED) provide moderate and low error protections,leading to moderate and high power savings, respectively.

In the D_SECDED mode, the JTEC-SQED scheme is selected, which uses duplication and HARQ-based HammingSEC-DED as the crosstalk avoidance and error control, respectively. JTEC-SQED is employed as it achieves high errorprotection, i.e., triple error correction and quadruple error detection, and it will be used in high-noise conditions. The drawback of this scheme is the increased bus power consumption dueto the switching of the duplicated wires and complex decoding algorithm.

In the power-saving modes, the crosstalk avoidance approachis switched to the shielding technique, while the error controlschemes used are HARQ-based Hamming SECDED and FECbased Hamming SEC for the S_SECDED and S_SEC modes,respectively. The S_SECDED mode enjoys error protection upto two error detections, while S_SEC has SEC, and thus, it willbe used in moderate and low-noise conditions, respectively. Inthese two modes, power reduction is achieved through the non-switching shield wires and non-active hardware logics at bothencoder and decoder due to simpler error control coding. Notethat shielding is an alternative crosstalk avoidance approachthat uses the same number of wires as duplication, and bothlimit the worst case CIBD to(1+2λ)τ0.

Encoder:

Figure 2: encoder

In this design have a 5 section:

  1. Selection for input data using MUX
  2. Temporary storage of input data for the retransmission process using retransmission buffer
  3. Padding the parity bit and data using flip flops
  4. Hamming SECDED encoder. In this the encoding use the (7+1, 3) hamming code is used. Where, hamming code is (7, 3) but we use the SECDCD technique so to modifies the code to (8, 3).
  5. We have work in the three modes. i.e., normal mode and two power-saving modes, namely, duplicated SECDED (D_SECDED), shielded SECDED (S_SECDED), and shielded SEC (S_SEC), respectively. So we use the Crosstalk control for control function.

Figure 3: crosstalk control

Hamming code:

The new technique is based on the use of the ECCs. A simple ECC takes a block of k bits and produces a block of n bits by adding n−k parity check bits. The parity check bits are XOR combinations of the k data bits. By properly designing those combinations it is possible to detect and correct errors. As an example, let us consider a simple Hamming code with k = 4 and n = 7. In this case, the three parity check bits p1, p2, p3 are computed as a function of the data bits d1, d2, d3, d4 as follows:

p1 = d1 ⊕ d2 ⊕ d3

p2 = d1 ⊕ d2 ⊕ d4

p3 = d1 ⊕ d3 ⊕ d4.                                                              (1)

The data and parity check bits are stored and can be recovered later even if there is an error in one of the bits. This is done by re-computing the parity check bits and comparing the results with the values stored. In the example considered, an error on d1 will cause errors on the three parity checks; an error on d2 only in p1 and p2; an error on d3 in p1 and p3; and finally an error on d4 in p2 and p3.Therefore, the data bit in error can be located and the error can be corrected. This is commonly formulated in terms of the generating G and parity check H matrixes. For the Hamming code considered in the example, those are

 

Encoding is done by computing y = x • G and error detection is done by computing s = y • HT, where the operator • is based on module two addition (XOR) and multiplication. Correction is done using the vector s, known as syndrome, to identify the bit in error. The correspondence of values of s to error position is captured in Table I. Once the erroneous bit is identified, it is corrected by simply inverting the bit.

Decoder:

Figure 4: decoder

In this have a 6 section for the decoding process.

  1. First the data are spilt in to the 2 copies of A and B. using f/f.s block
  2. Syndrome calculation. In this is used to error detection process using the H matrix.
  3. Then the parity bit is get into the syndrome calculation block to Odd/Even block. This block is checking the parity error. If error means give the output as high else low.
  4. The error correction does in the error correction block with the input of k bits of data and h bits of parity bit.
  5. Then the correction bit are compare in the comparator block and the decision logic for SECDED and JTEC-SQED are taken using parity bits.
  6. The retransmission request is selected by using mode and output flit is selected by MSB bit of the mode signal and output of the JTEC-SQED logic.

Advantages:

  • Low power consumption

Software implementation:

  • Modelsim
  • Xilinx ISE