10T SRAM Using Half-VDDPrecharge andRow-Wise Dynamically Powered ReadPort for Low Switching Powerand Ultralow RBL Leakage
We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell’s supply voltage, and is allowed to charge and discharge according to the stored data bit. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. RBL increases toward the VDD level for a read-1, and discharges toward the ground level for a read-0. Virtual power rails have the same value of the RBL precharging level during the write and the hold mode, and are connected to true supply levels only during the read operation. Dynamic control of virtual rails substantially reduces the RBL leakage. The proposed 10T cell in a commercial 65 nm technology is 2.47×the size of 6T with β=2, provides 2.3×read static noise margin, and reduces the read power dissipation by 50% than that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and (ION/IOFF) is greatly improved compared with the 6T BL leakage. The overall leakage characteristics of 6T and 10T are similar, and competitive performance is achieved. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
SRAM cell must robustly operate under hold, read, andwrite mode. An SRAM cell uses the positive feedback ofcross-coupled inverters (INVs) to store a single bit of information in a complementary fashion. Access transistors providethe mechanism for the read and write operation. Before everyaccess, column BL pair (BL and BLB) is precharged to thesupply voltage. For the write operation, one of the prechargedBLs is discharged through the write driver.
Figure 1: Conventional 6T SRAM read. (a) Column of M bit-cells during read. (b) Top: hold and read SNM butterfly curve (with worst case noise polarity during hold). Bottom: transient behavior showing read disturbance
Fig. 1(a) shows a single column ofM6T SRAM cells,where one cell is accessed in read mode with data=0(Qa=0), while other M−1 cells are in the hold mode.Leakage components are labeled, and for the worst caseleakage, all M−1 cells store data=1(Qu=1).Iread flowsfrom BL to the VSSthrough AL and NL of the accessed cell,and the BL voltage is decreased. The unaccessed cell on theBL exhibits BL leakage.IuLeak0 is the main component ofBL leakage whileIuLeak1 is negligible, as VDSof AR of theunaccessed cell is large, whileVDSof its AL is very small(varies from 0 toVBL). These leakage components decreasethe differential BL voltage development. As there are a largenumber of cells in a single column, the worst case BL leakagecan decrease BLB voltage enough to make an erroneous read.Thus,Iread must be greater than(M−1)×IuLeak0,whereMis the number of cells in a single column.
Figure 2: SRAM read ports (a) 6T. (b) 8T.(c) 9T.(d) 9T.(e) 10T.
In essence, 6T SRAM has conflicting read and write requirements and transistor sizing cannot be done independently.Also, 6T has inherit RSNM problem as the read currentpasses through the cell internal node, and it furtherdegrades withVDDscaling. Also, being considered asbaseline design, 6T has overall a higher power dissipation,and higher BL leakages, as the low power techniques employa certain mechanism to lower the dynamic power dissipation,e.g., charge sharing and hierarchical BL andthe leakages (by employing virtual rails). The readport of 6T SRAM cell is shown in Fig. 2(a) that highlightsthe internal node Q in the read current path. Many alternativebitcells and techniques have been proposed in the literature toimprove SRAM cell stability, reduce the leakage currents, andachieve low power operation compared with the conventional6T design.
An 8T SRAM cell adds a separate 2T read port, shownin Fig. 2(b), and necessarily solves the problem of readstability. Internal nodes are isolated from the read current path,and thus a high RSNM is achieved. Also, sizing of 8T readport can be done independently without affecting the writeoperation.
In 6T SRAM read operation, one of the BL stays at theVDDwhile the other decreases byVBLamount. However, in thecase of 8T SRAM, there is only one BL (RBL) and it eitherdecreases or stays at theVDDlevel depending on the bit read.Now, the sensing of SE BL can be done using different circuitssuch as: 1) domino sensing that requires full VDDswing ONthe local-BL; 2) psuedo-differential that requires a referencesignal; and 3) ac coupled sensing that requires the use ofcapacitors. Using a reference-based sense amplifier, onlya small voltage difference is required.
- Power consumption is high
We present our halfVDDprecharge and chargerecycling technique for low power read operation. A 4T readport is designed to employ the proposed technique. ReadBL (RBL) is charged and discharged through the read portaccording to the state of stored bit. Read port is poweredby virtual power rails that run horizontal and are shared bythe cells of a word. The dynamic control of read port powerrails reduces the RBL leakage substantially.
Figure 3: Proposed 10T SRAM cell with row-wise read port dynamic power lines
The proposed 10T SRAM cell with SE RBL is shownin Fig. 3. We have added a 4T read port to the 6T cell todecouple the internal nodes during the read operation. Readport consists of an INV P1-N1 driven by node QB, and atransmission gate (TG) P2-N2. The output (Z) of the INVis connected to RBL during the read operation through TG,which is controlled by (read) control signals. Furthermore,read port is powered by virtual power rails, VVDDandVVSS,which are dynamically controlled. These virtual power rails(control signals) run horizontally, and have the true rail valuesonly during the read operation. For the RBL leakage reduction,both the virtual rails have the same level as the precharge levelof RBL.
- The 10T SRAM cell using an INV and a TG has been proposed earlier. However, our proposed 10T scheme is different from the previous design in the following aspects. The previous INV+TG-based 10T cell was application specific, while our proposed design is generic.
- We have used the dynamically controlled power rails for the read port.
- We precharge RBL at VDD/2, while the previous 10T design eliminated the precharge phase, and used INV to fully charge or discharge the RBL.
- The basic read technique of both the designs is completely different. The main idea of the proposed design is “the charging or the discharging of the read BL from VDD/2 for every read operation.” The previous design either discharges from VDD to VSS, or charges from VSS to VDD.
- A powerful INV was used previously to produce full VDD swing on the RBL. In the proposed design, RBL is precharged at VDD/2, and only a small voltage difference (comparable with 6T) is produced for every read cycle.
- In the proposed design, for every read cycle the RBL will exhibit some change (positive or negative) from its precharged value of vdd/2. However, the RBL would not change for consecutive similar bit reads. RBL would change only if consecutive read bits are different.
- Power consumption is low
- Tanner tool