A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression
Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancelation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancelation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm2 of the die area. The HD-LDO operates with an input voltage range of 1.43–2.0 V and an output voltage range of 1.0–1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
A typical analog LDO (ALDO) regulator, as shown in Fig.1, is a second-order system with a high gain error amplifier A0and an output power transistor M0. An external output capacitor COUT and its equivalent series resistance (RESR)are added for the compensation of the loop. This configuration has been used in many applications, but it suffers from several issues. The capacitor COUT introduces a zero to ensure sufficient loop phase margin, but the RESR increases the output ripple voltage during the load transients. The output load current variations move the ALDO output pole, which changes the ALDO phase margin [Fig. 1(b)]. The RESR of the capacitor is also not well controlled and can vary widely for different types of capacitors. Given these factors, the frequency stability of an analog LDO significantly depends on the load current as well as the external capacitor COUT and its RESR.
Figure 1: Conventional analog LDO (a) block diagram and (b) its frequency response
Several methods have been proposed in the analog LDO linear regulator to eliminate these issues. An approach proposed to reduce these deficiencies is to use a tracking zero circuit to cancel the load-dependent LDO output pole. However, this approach suffers from a mismatch in the pole-zero cancelation as the output pole varies linearly with the load current while the introduced zero is a nonlinear function of the load current. An alternative method is to generate an internal fixed zero at the output node of the resistive feedback using frequency dependent voltage controlled current source. However, this method cannot be realizable in the resistive feedbackless regulator. The error amplifier output pole location is required to be at higher frequency to circumvent stability and load transient ripple issues, which limits the power transistor M0 size resulting in a lower output maximum load current.
Figure 2: Conventional synchronous DLDO. (a) Block diagram. (b) Loaddependent output ripple
Digital LDO (DLDO) regulator is an innovative approach that uses digital controller to minimize the external compensation network. Block diagram of a synchronous DLDO is shown in Fig. 2(a). An analog-to-digital converter (ADC) is used to digitize the output voltage. The generated error voltage is fed to the input of the digital controller to generate the compensation digital code for the output power digital to-analog converter (DAC). DLDO offers advantages in terms of integration, scalability, size, programmability, and stability over a wide range of load current variations, and a lower sensitivity to process variations. In most of the recent DLDO implementations, output transistor in power DAC operates in the linear (triode) region to reduce the silicon area. However, the triode region operation yields poor power supply rejection (PSR) and lower efficiency at higher loads. An additional feedback loop is implemented to improve PSR. However, the additional loop increases the complexity and reduces efficiency.
Although the DLDO regulators show better transient and stability performance over a wide load range, in the steady state condition their output voltage suffers from load current dependent ripple , . The DLDO supplies current to the output load in discrete steps, and in steady-state conditions, digital loop compensation causes voltage ripple at the output. If the output voltage changes by more than one ADC LSB, the feedback digital error signal changes resulting in new controller code. This causes the analog output voltage to cycle continuously around the regulated dc output voltage level to provide the required output load current. The output ripple voltage of a synchronous DLDO for various load currents is shown in Fig. 2(b). In Fig. 2(b), it is assumed, k IDAC−LSB<ILOAD<(k+1)IDAC−LSB and Ierr =(ILOAD− k IDAC−LSB),where IDAC−LSB is the current resolution of the power DAC and k is an integer number. Traces labeled by ILOAD−a, ILOAD−b, and ILOAD−c represent output ripple voltages when Ierr <0.5IDAC−LSB, Ierr ≈0.5IDAC−LSB, and Ierr >0.5IDAC−LSB, respectively. This result shows that the output ripple voltage is a function of the load current. The ripple period depends on the control loop parameters such as loop response time, output node capacitance, ADC resolution, output load current, and the clock frequency. This ripple generates supply noise that can impact sensitive analog and mixed-signal circuits powered by the DLDO.
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a hybrid DLDO (HD-LDO) regulator utilizing a DLDO regulator in parallel with a wideband ripple cancelation amplifier (RCA) to cancel the output ripple associated with the switching ripple due to the DLDO. During the steady-state operation, the RCA supplies the error current between the DLDO output current and the required load current, and suppresses the output voltage ripple. The maximum output current of the RCA is limited to the minimum current step resolution of the DLDO, which is typically less than 1% of the maximum load current. Low current requirement simplifies the RCA design, which results in a fast RCA feedback loop without the use of complex compensation techniques of the conventional analog linear regulator. To enable fast load transient, a gear-shift controller is designed based on dynamic load estimation. In a typical DLDO, large output capacitor suppresses the output voltage ripple, whereas in the proposed HD-LDO the RCA suppresses the output voltage ripple without output capacitance.
The architectural block diagram of the proposed HD-LDO is shown in Fig. 3(a). A hybrid combination consists of the digital loop with DLDO in parallel with the analog loop with the RCA. The analog loop compares the output voltage (VOUT) with the reference voltage (VREF) and generates the current IRCA proportional to the error voltage between VREF and VOUT. The DLDO senses the linear stage current IRCA in every clock cycle and changes the DLDO output current (IDLDO) to force the IRCA to zero. At steady-state condition, due to the power DAC quantization error, the output voltage cycles around the reference output voltage level. The analog loop is formed by a wideband, high gain, low-power amplifier connected in a unity-gain configuration and supplies the residual current within one LSB of the DLDO to reduce the output voltage ripple. The analog regulation and digital regulation continuously track and minimize the output voltage error and linear stage current, respectively, and an accurate output regulation is achieved.
Figure 3: Block diagram of proposed HD-LDO.(a) Architecture. (b) Structural
Ripple Cancelation Amplifier:
In the proposed hybrid architecture, the analog loop is in parallel with the DLDO to cancel the quantization error of the DLDO and reduce the ripple caused by the limit-cycle behavior of the DLDO. The analog loop operates within one LSB of the DLDO output and its current is bound −IDAC−LSB <IRCA <IDAC−LSB. The ripple cancelation amplifier output current IRCA can be sourced or sunk depending on the digital regulator output current.
Figure 4: Class-AB folded cascode RCA
Feedback Analog-to-Digital Converter:
The ADC in the DLDO converts the output current of the RCA into the digital equivalent for the PID controller input. To reduce the power consumption, a 2-bit ADC is selected. The output current of the RCA is sensed by a resistor RSEN, which converts RCA output current into a voltage VSEN. The negative feedback loop of the RCA forces the HD-LDO output voltage VOUT equal to VREF. When the RCA sources/sinks current to/from the load, VSEN becomes positive/negative. Voltage VSEN is compared using three clocked comparators of the 2-bit ADCasshowninFig.5.SignalD2 is low for VSEN>VTH and D0 becomes high for VSEN <−VTH. The output D1 of comparatorC1 becomes low for VSEN >0 and high for VSEN<0. Therefore,D1 carries information about the RCA output current direction.
Figure 5: 2-bit flash ADC.
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