A 0.45 V 147–375 nW ECG Compression ProcessorWith Wavelet Shrinkage and AdaptiveTemporal Decimation Architectures
This paper presents a real-time electrocardiogram (ECG) data compression processor with improved energy efficiency while maintaining high accuracy and real-time operation. Wavelet shrinkage is exploited to filter the noise and achieve sparse ECG signal representation. Adaptive temporal decimation is proposed to achieve configurable processing to adaptively reduce the data amount and computational activities for further power reduction. Modified Huffman and run-length wavelet source coding (MHRLC) is also designed to represent wavelet coefficients with optimized average code length and reduced memory requirement. Fabricated in 0.18-µmCMOS, the ECG processor is implemented with customized near-threshold digital logics for minimum energy operation. The prototype was fully validated with the MIT-BIH Arrhythmia database. The proposed architecture of this paper analysis the logic size, area and power consumption using tanner tool.
WEARABLE fitness tracking devices open up the possibility of recording and analyzing long-term data thatare improving today’s healthcare systems. The continuouslygenerated health data (withvarious pieces of physiologicalinformation over time) can help detect health status, suggest lifestyle qualities, and discover symptoms of illnesses. Savingpower is an important design aspect of such battery-poweredsystems, not only for increased operation time, but alsofor providing more functions and higher performance at thesame power budget. Various wireless wearable devices arereported for electrocardiogram (ECG) long-term monitoring, typically with analog front end, analog-to-digitalconverter, processor, wireless, and power supply/managementmodules. Specialized digital processor architecture can significantly improve power efficiency compared with generalpurpose processor architecture. For this advantage,specialized architectures for ECGcharacteristic point detection are published, a fully digital front endis even exploited for further power saving. As demonstrated, the system power can also be effectivelyreduced by lowering the wireless activities, which can beachieved by introducing alocal signal processorto preprocessthe acquired data. Power savings can be achieved as long asPcomp+Ptx/CR<Ptx,wherePcompis the extra computationalpower,Ptx is the power for wireless transmission, and CRisthe data compression ratio.
Under a limited power budget, data storage space, and/ordata transmission bandwidth, the system can be designed totransmit only the detection result with local ECG characteristicpoint detection processors to effectively reduce thewireless transmission power. Yet, this approach prohibits thepossibility for further medical validation and analysis, and isconsequently undesirable for certain usages. For the ECG datacompression processors, the ECG data areencoded to achieve compression ratios (CRs) of 2.38 and 2.43,respectively. Nonetheless, the lack of flexibility in CR canresult in sub-optimal system performance when only a portionof the signal is of interest with high accuracy requirement.In this case, the system power can be further optimized bymainly recording the signals of interest with high fidelity,e.g., infrequently occurring symptoms or signals happeningin a specific period of time, while leaving other parts of thesignal to be highly compressed. It can also improve the systemadaptability to varying requirements, including CR, accuracy,and power efficiency.
- Power consumption is high
In the proposed system paper investigates the design of a specialized ECGcompression processor usingwavelet shrinkage (WS), adaptivetemporal decimation (ATD),and a combinedmodified Huffmanand run-length wavelet source coding (MHRLC)architectures.Wavelet transform (WT) architecture is optimized for lowswitching activity. WS is exploited to filter the noise andachieve sparse ECG signal representation. The type of waveletis systematically compared for accuracy, low hardware cost,and improved CR. ATD is proposed to achieve configurableprocessing to adaptively increase CR and reduce circuitswitching activities. MHRLC is also designed for coding thewavelet coefficients with optimized average code length andreduced the memory requirement. A set of energy-efficientlow-voltage digital logic circuits optimized for low-frequencyoperation are custom designed and employed. Measurementresults show that the proposed ECG processor achieves ultralow-power consumption and a wide range of CR for configurable lossless or lossy compressions while maintaining gooddata recovery accuracy and real-time operation.
Overview of ECG datacompressionprocessor:
Fig. 1 shows the block diagram of the proposed ECGdata compression processor, which is composed of three mainmodules: ATD, WS, and MHRLC. The processor consists ofan ECG readout front-end, ECG processor and a back-endwireless module for data transmission. This paper focuses onthe algorithm and implementation of the ECG data compression core under a sub-µW power budget.
Figure 1: Proposed ECG processor architecture.
The processor supports a 12-bit signed fixed-point numberas the ECG input, and outputs the encoded signal with frameand symbol coding protocol. The signal data representationis marked by (Signedness, Word Length, Fractional Length).The ECG signal and wavelet coefficients are represented in12 bits (8 integer bits and 4 fractional bits). The external clockcan be flexibly tuned from 60 Hz to 1 kHz. Notice that thebaseline wander removal and noise filtering are expected to beperformed in signal acquisition front end before the signal isfed into the proposed processor, as in most ECG acquisitionsystems.
Fig. 1 shows the three main modules of the proposedprocessor. WT type (mother wavelet) and architecture arefirst selected and designed, balancing the accuracy, CR, andhardware efficiency. WS is optimized to enable global threshold estimation without PRD degradation. ATD is exploited todecimate the ECG signal adaptively by discriminating the QRSwave and P/T waves. The sparse wavelet coefficients are thencompressed using the MHRLC optimized for the application.The detailed description of the modules is presented asfollows.
Adaptive Temporal Decimation:
The ECG signal temporally consists of the P/T waves(4 to 13.5 Hz) and QRS waves (8 to 27 Hz), while thecommon sampling rates are 128 Hz, 250 Hz, 360 Hz, 500 Hz,720 Hz, and 1 kHz. This frequency difference can be exploitedfor reducing the intersample redundancy using decimation,and the data can be reconstructed at the recover side usinginterpolation and resampling methods. By considering thedifferent frequency ranges between the QRS complex andP/T waves, ATD is proposed to decimate high frequency wave(QRS complex) and low frequency wave (P/T waves) withdifferent rates. The decimation rate can be 1 (no decimation)or 2 for QRS waves, and can be configured to be 2, 4, 8, 16,or 32 for P/T waves.
Figure 2: Adaptive temporal decimation circuit
2) Wavelet Transform Architectural Optimization:Fig. 3(a)shows the “à trous” algorithm WT architecture. Zeros areinserted between different FIR filter coefficients, and the number of inserted zero increases by a power of 2 for each waveletscale. It can generate wavelet coefficients of the same samplingrate to input signal, but it demands a huge number of datastorage elements and processing to the wavelet coefficientsof redundant information increases circuit switching activity.Instead, the Mallat’s algorithm in Fig. 3(b) is chosen. It’sdown-sampling architecture removes information redundancyof wavelet coefficients and thus reducing computation amountafterward. The FIR filter order is short thereby saving thehardware resources. With the Mallat’s algorithm, the inputsignal is decomposed and decimated to five scalesd1,d2,d3,d4, anda4, and the sampling period of the scales are 2, 4,8, 16, and 16 clock cycles, respectively.
Figure 3 : Wavelet decomposition architectures and the perfect reconstruction algorithm. (a) “Algorithme à trous” for wavelet decomposition. (b) Mallat’s
3) Shrinkage Architecture and Optimization: WT linearlytransforms the signal to wavelet coefficients with the energycompaction characteristic and generates only small portionsof large-valued coefficients. Sparse signal representation isproduced by applying thresholding to insignificant coefficients.As shown in Fig. 8, the ECG signalecg_d is fed intothe WT block for processing only the decimated samplesaccording to the ATD timing signala_en.Thed1–d4 scalesare real-time estimated and thresholds are adaptively applied.The stationary points (also called peak sample) in scaled1are detected by extracting the larger sample from neighboring samplings. The peak samples are further processed forthreshold estimation. The wavelet coefficients of scale d1–d4are sparsified with thresholds except the scale a4 for itssmall data rate and insignificant content amount.
Figure 4: Proposed WS architecture
- Power consumption is low
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